The UNIVAC 1100/2200 series is a series of compatible 36-bit computer systems, beginning with the UNIVAC 1107 in 1962, initially made by Sperry Rand. The series continues to be supported today by Unisys Corporation as the ClearPath Dorado Series. The solid-state 1107 model number was in the same sequence as the earlier vacuum-tube computers, but the early computers were not compatible with the solid-state successors.
|014||X12/A0||Overlap (X or A)|
|...||...||Overlap (X or A)|
|017||X15/A3||Overlap (X or A)|
The 128 registers of the high-speed "general register stack" ("integrated circuit registers" on the UNIVAC 1108 and UNIVAC 1106 models), map to the current data space in main storage starting at memory address zero. These registers include both user and executive copies of the A, X, R, and J registers and many special function executive registers.
The table on the right shows the addresses (in octal) of the user registers.
There are 15 index registers (X1 ... X15), 16 accumulators (A0 ... A15), and 15 special function user registers (R1 .. R15). The 4 J registers and 3 "staging registers" are uses of some of the special function R registers.
One interesting feature is that the last four index registers (X12 ... X15) and the first four accumulators (A0 ... A3) overlap, allowing data to be interpreted either way in these registers. This also results in four unassigned accumulators (A15+1 ... A15+4) that can only be accessed by their memory address (double word instructions on A15 do operate on A15+1).
Prior to the UNIVAC 1107, UNIVAC produced several vacuum-tube-based machines with model numbers from 1101 to 1105. These machines had different architectures and word sizes and were not compatible with each other or with the 1107 and its successors. They all used vacuum tubes and many used drum memory as their main memory. Some were designed by Engineering Research Associates (ERA) which was later purchased and merged with the UNIVAC company.
The UNIVAC 1101, or ERA 1101, was a computer system designed by ERA and built by the Remington Rand corporation in the 1950s. It was never sold commercially. It was developed under Navy Project 13, which is 1101 in binary. The UNIVAC 1102 or ERA 1102 was designed by Engineering Research Associates for the United States Air Force. The 36-bit UNIVAC 1103 was introduced in 1953 and an upgraded version (UNIVAC 1103A) was released in 1956. This was the first commercial computer to use core memory instead of the Williams tube. The UNIVAC 1105 was the successor to the 1103A, and was introduced in 1958.
The UNIVAC 1104 system was a 30-bit version of the 1103 built for Westinghouse Electric, in 1957, for use on the BOMARC Missile Program. However, by the time the BOMARC was deployed in the 1960s, a more modern computer (a version of the AN/USQ-20, designated the G-40) had replaced the UNIVAC 1104.
These machines had a common architecture and word size. They all used transistorized electronics and integrated circuits. Early machines used core memory (the 1110 used plated wire memory) until that was replaced with semiconductor memory in 1975.
The UNIVAC 1107 was the first solid-state member of Sperry Univac's UNIVAC 1100 series of computers, introduced in October 1962. It was also known as the Thin-Film Computer because of its use of thin-film memory for its register storage. It represented a marked change of architecture: unlike previous models, it was not a strict two-address machine: it was a single-address machine with up to 65,536 words of 36-bit core memory. The machine's registers were stored in 128 words of thin-film memory, a faster form of magnetic storage. With six cycles of thin-film memory per 4 microsecond main memory cycle, address indexing was performed without a cycle time penalty. Only 36 systems were sold.
The core memory was available in 16,384 36-bit words in a single bank; or in increments of 16,384 words to a maximum of 65,536 words in two separately accessed banks. With a cycle time of 4 microseconds, the effective cycle time was 2 microseconds when instruction and data accesses overlapped in two banks.
The 128-word thin-film memory general register stack (16 each arithmetic, index, and repeat with a few in common) had a 300-nanosecond access time with a complete cycle time of 600 nanoseconds. Six cycles of thin-film memory per core memory cycle and fast adder circuitry permitted memory address indexing within the current instruction core memory cycle and also modification of the index value (the signed upper 18 bits were added to the lower 18 bits) in the specified index register (16 were available). The 16 input/output (I/O) channels also used thin-film memory locations for direct-to-memory I/O memory location registers. Programs could not be executed from unused thin-film memory locations.
Both UNISERVO IIA and UNISERVO III tape drives were supported, both of which could use either metallic (UNIVAC I) or mylar tape.
The FH880 drum memory unit was also supported as a spooling and file-storage media. Spinning at 1800 RPM, it stored approximately 300,000 36-bit words.
The 1107, without any peripherals, weighed about 5,200 pounds (2.6 short tons; 2.4 t).
Univac provided a batch operating system, EXEC I. Computer Sciences Corporation was contracted to provide a powerful optimizing Fortran IV compiler, an assembler named SLEUTH with sophisticated macro capabilities, and a very flexible linking loader.
The 1108 was introduced in 1964. Integrated circuits replaced the thin-film memory that the UNIVAC 1107 used for register storage. Smaller and faster cores, compared to the 1107, were used for main memory.
In addition to faster components, two significant design improvements were incorporated: base registers and additional hardware instructions. The two 18-bit base registers (one for instruction storage and one for data storage) permitted dynamic relocation: as a program got swapped in and out of main memory, its instructions and data could be placed anywhere each time it got reloaded. To support multiprogramming, the 1108 had memory protection using two base and limit registers, with 512-word resolution. One was called the I-bank or instruction bank, and the other the D-bank or data bank. If the I-bank and D-bank of a program were put into different physical banks of memory, a 1/2 microsecond advantage accrued, called "alternate bank timing." The 1108 also introduced the Processor State Register, or PSR. In addition to controlling the Base Registers, it included various control "bits" that enabled the various Storage Protection features, allowed selection of either the User or Exec set of A, X & R registers, and enabled "Guard Mode" for user programs. Guard Mode prevented user programs from execution of Executive Only "privileged" instructions, and from accessing memory locations outside the program's allocated memory.
Additional 1108 hardware instructions included double precision arithmetic, double-word load, store, and comparison instructions. The processor could have up to 16 input/output channels for peripherals. The 1108 CPU was, with the exception of the 128-word (200 octal) ICR (Integrated Control Register) stack, entirely implemented via discrete component logic cards, each with a 55-pin high density connector, which interfaced to a machine wire wrapped backplane. Additional hand applied twisted pair wiring was utilized to implement backplane connections with sensitive timing, connections between machine wire wrapped backplanes, and connections to the I/O channel connector panel in the lower section of the CPU Cabinet. The ICR (Integrated Control Register) stack was implemented with "new" integrated circuit technology, replacing the thin film registers on the 1107. The ICR consisted of 128 38-bits, with a half-word Parity Bit calculated and checked with each access. The ICR was logically the first 128 memory addresses (200 Octal), but was contained in the CPU. The core memory was contained in a one or more separate cabinet(s), and consisted of two separate 32K modules, for a total capacity of 64K 38-bit words (36-bits data and a Parity Bit for each 18-bit half-word). The basic cycle time of the core memory was 750 ns, and the supporting circuitry was implemented with the same circuit card/backplane technology as the 1108 CPU.
Just as the first UNIVAC 1108 systems were being delivered in 1965, Sperry Rand announced the UNIVAC 1108 II (also known as the UNIVAC 1108A) which had support for multiprocessing: up to three CPUs, four memory banks totaling 262,144 words, and two independent programmable input/output controllers (IOCs). With everything busy, five activities could be going on at the same moment: three programs running in the CPUs and two input/output processes in the IOCs. One more instruction was incorporated: test-and-set, to provide for synchronization between the CPUs.
Although a 1964 internal study indicated only about 43 might sell, in all, 296 processors were produced.
The 1108 II, or 1108A, was the first multiprocessor machine in the series, capable of expansion to three CPUs and two IOCs (Input/Output Control Units). To support this, it had up to 262,144 words (four cabinets) of eight-ported main memory: separate instruction and data paths for each CPU, and one path for each IOC. The memory was organized in physical banks of 65,536 words, with separate odd and even ports in each bank. The instruction set was very similar to that of the 1107, but included some additional instructions, including the "Test and Set" instruction for multiprocessor synchronization. Some models of the 1108 implemented the ability to divide words into four nine-bit bytes, allowing use of ASCII characters. Most 1108A configurations included one or two CPUs, each with eight or (optionally) 16 36-bit parallel I/O channels, and two or three 64K core memory cabinets. Three CPU systems, with four core memory cabinets were the exception due to cost considerations. The IOC was a separate cabinet that contained 8 or (optionally) 16 additional I/O channels to support configurations with very large Mass Storage requirements. A very limited number of IOCs were produced, with United Air Lines (UAL) being the primary customer.
The UNIVAC Array Processor, or UAP, was produced in even more limited numbers that the IOC. It was a custom-built, stand-alone math coprocessor to the 1108A system. The UAP, at its most basic level, consisted of four 1108A arithmetic units, and associated control circuitry, contained in a standalone cabinet almost identical to the 1108A CPU. The UAP was physically and logically situated between two 1108A multiprocessor systems. It was capable of directly addressing and interfacing to the four 65K core memory cabinets of two independent 1108A systems. It was capable of executing a number of array-processing instructions, the most important being fast Fourier transform (FFT). At a simplified level, one of the 1108A CPUs would move data arrays into core memory, and send the UAP an instruction packet, containing the function to be executed, and the memory address(es) of the data array(s), across a standard I/O channel. The UAP would then perform the operation, totally independent of the CPU(s), and, when the operation was complete, "interrupt" the originating CPU via the I/O channel. A very small number of UAPs were built, with Shell Oil Company being (likely) the only customer. The UAPs were installed in Shell's Houston Data Center, and were used to process seismic data.
When Sperry Rand replaced the core memory with semiconductor memory, the same machine was released as the UNIVAC 1100/20. In this new naming convention, the final digit represented the number of CPUs (e.g., 1100/22 was a system with two CPUs) in the system.
The 1107 and early 1108 machines were aimed at the engineering/scientific computing community, so much so that the 1100 Series User Group was named the UNIVAC Scientific Exchange, or USE. The operating systems were batch oriented, with FORTRAN and (to a much lesser extent) ALGOL being the most commonly used languages. As the market for commercial computing became more mature, these operating systems were no longer able to meet the growing demand for business computing, where applications were commonly written in COBOL. UNIVAC responded to this change in the market with the 1108A multiprocessor system and with the EXEC 8 operating system. Where engineering and scientific programs could often be "compute bound" (i.e. utilizing the entire CPU and core memory), business applications, typically written in COBOL, were almost always "I/O bound" (i.e. waiting for I/O operations to complete). Instrumentation of the EXEC 8 operating system showed that, in a 1108A multiprocessor configuration, the CPU(s) were often in the "idle loop" as much as 50% of the time (see note below). Since CPU performance was not an issue in these applications, it made commercial sense to create a lower-priced, lower-performance system to address the rapidly growing commercial business market.
The UNIVAC 1106 was introduced in December 1969 and was absolutely identical to the UNIVAC 1108, both physically and in instruction set. Like the 1108, it was multiprocessor capable, though it appears that it was never supplied with more than two CPUs, and did not support IOCs. In fact, the only difference between an 1108A CPU and an 1106 CPU was a couple of timing cards. In order to keep costs low, an 1106 CPU could be ordered with as few as four word channels. This meant that only three I/O channels were available for peripheral subsystems, as channel 15 (the highest-numbered channel) was always, in both 1106 and 1108 systems, dedicated to the operator's console. Early versions of the UNIVAC 1106 were simply half-speed UNIVAC 1108 systems. Later Sperry Univac used a different memory system which was inherently slower and cheaper than that of the UNIVAC 1108. Sperry Univac sold a total of 338 processors in 1106 systems.
When Sperry Rand replaced the core memory with semiconductor memory, the same machine was released as the UNIVAC 1100/10.
The UNIVAC 1110 was the fourth member of the series, introduced in 1972.
The UNIVAC 1110 had enhanced multiprocessing support: sixteen-way memory access allowed up to six CAUs (Command Arithmetic Unit, the new name for CPU and so called because the CAU no longer had any I/O capability) and four IOAUs (Input Output Access Units, the name for separate units which performed the I/O channel programs). The 1110 CAU expanded the memory address range from the 18-bits (1108 and 1106) to 24-bits, allowing for up to 16 million words of addressable memory. The core memory used on the 1108/1106 systems was replaced with faster plated wire memory. Each memory cabinet contained eight independent 8K plated wire memory modules, or 64K for the entire cabinet. As with the 1108/1106, there was a maximum of four 64K cabinets per system. The 1110 also had 'Extended Memory' cabinets accessible in a 'daisy chain' arrangement to augment main storage. It was possible to utilize the 1108 64K core memory cabinets as Extended Storage, but in most systems utilized, the larger, less expensive 131K memory cabinets from the 1106 system. Up to eight Extended Memory cabinets were allowed, for a maximum of one million words of Extended Storage. An ESC (Extended Storage Controller) was required for each pair of memory cabinets to provide the physical connection, and address translation, from the 1110 CAUs and IOAU(s).
The minimum configuration for a 1110 system was two CAUs and one IOAU. The largest configuration, 6x4 was only used by NASA. The 1110 CAU was the first pipelined processor to be designed by UNIVAC. The CAU could have as many as four instructions in various stages of execution at any given instant. The IOAU was completely separate, both physically and logically from the CAU, and had its own access path to the various Main and Extended Memory Modules. This allowed I/O operations to be independent from the compute operations, no longer "stealing" memory cycles from CAU(s). The IOAU included 8 (optionally 16 or 24) 1108/1106 compatible 36-bit Word Channels, and also included the Hardware Maintenance Panel. Pictures/illustrations of a 1110 system typical showed the IOAU Maintenance Panel, as the CAU cabinet had no indicator lights. The IOAU Maintenance Panel could display the various CAU registers from one or two associated CAU(s). The 1110 CAU also introduced an extension to the instruction set of 'Byte Instructions'. The major components of the 1110 system, the CAU, IOAU and Main Memory cabinets were designed using the same 55-pin high density card connectors, and machine wire wrapped backplane(s) as the 1108/1106. The discrete component logic used by the older systems was replaced by transistor–transistor logic (TTL) integrated circuits (see Note, below). The CAU was an extremely complex unit, utilizing over 1000 cards.
When Sperry Rand replaced the plated wire memory with semiconductor memory, the same machine was released as the UNIVAC 1100/40. In this new naming convention, the final digit represented the number of CPUs in the system. The 1100/40 utilized a new Main Memory cabinet, replacing the 8K plated wire memory modules with 16K static RAM modules (based on 1024x1-bit static RAM chips), for a total of 131K per cabinet. This allowed expansion of the Main Memory to a maximum of 524K. As with the 1110, the 1100/40 CAU had four base and limit registers, so a program could access four 64k banks. New instructions were added to allow a program to change the contents of the banks, rather than the banks being fixed when the program was prepared
Sperry Rand sold a total of 290 processors in 1110 systems.
Note: TTL Integrated circuits used in 1110 (1100/40) CAU, IOAU and Main Memory cabinets were ceramic 14-pin DIPs, where pins 4 and 10 were +5 volts and ground respectively: state-of-the-art in 1969.
#3007500 - Integrated Circuit - IC32, Hex Inverter #3007501 - Integrated Circuit - IC33, Quad 2 Input NAND #3007502 - Integrated Circuit - IC34, Triple 3 Input NAND #3007503 - Integrated Circuit - IC35, Dual 4 Input NAND with Split Output #3007504 - Integrated Circuit - IC36, 8 Input NAND with Split Output #3007505 - Integrated Circuit - IC37, Quad 2 Input NOR #3007506 - Integrated Circuit - IC38, Dual And-Or Inverter-2 Wide OR, 2, 2 Input AND, with Split Output #3007507 - Integrated Circuit - IC39, Triple FLIP-FLOP with Set, Over-Ride, and Reset #3007508 - Integrated Circuit - IC40, Dual FLIP-FLOP, "D" Type #3007509 - Integrated Circuit - IC41, AND-OR Inverter-4 Wide OR, 2, 2, 3, 4 Input AND #3007603 - Integrated Circuit - IC50, Quad Two-Input Line Driver Part Numbers beginning with "3" originated in the Univac Blue Bell (Philadelphia), PA location. Part numbers beginning with "4" originated in the Roseville (St. Paul), MN location. Purchased Components group was in Blue Bell.
In 1975, Sperry Univac introduced a new series of machines with semiconductor memory replacing core, with a new naming convention:
An upgraded 1106 was called the UNIVAC 1100/10. In this new naming convention, the final digit represented the number of CPUs or CAUs in the system, so that, for example, a two-processor 1100/10 system was designated an 1100/12. An upgraded 1108 was called the UNIVAC 1100/20.
An upgraded 1110 was released as the UNIVAC 1100/40. The biggest change was the replacement of the Type 7015 64K Plated Wire Memory cabinet with a new Type 7030 131K solid state (static RAM) Memory Cabinet. The allowed Main Storage to be expanded from maximum of 262K to a maximum of 524K. The Type 7030 Main Memory cabinet still contained eight separate Memory Modules, but they were now 16K (38-bit words, 36 Data and 2 Parity), instead of 8K each. The Type 7013 131K Core Memory Cabinet (originally used on the later 1106 Systems as Main Storage) was also replaced with a Solid-State Memory Cabinet, based on Intel 1103A DRAM.
The UNIVAC 1100/80 was introduced in 1979. It was intended to combine 1100 and 494 systems. As with the 1100/10, 1100/20 and 1100/40, the final digit represented the number of CAUs in the system.
The 1100/80 introduced a high-speed cache memory - the SIU or Storage Interface Unit. The SIU contained either 8K, or (optionally) 16K 36-bit words of buffer memory, and was logically and physically positioned between the CAU(s)/IOU(s) and the (larger, slower) Main Memory units. The first version of the 1100/80 system could be expanded to a maximum of two CAUs, and two IOUs. A later version was expandable to four CAUs and four IOUs. The SIU control panel of the updated 1100/80 (pictured above) was able to logically and physically partition larger Multi-Processor configurations into completely independent systems, each with its separate Operating System. The CAU was capable of executing both 36-bit 1100 series instructions, and 30-bit 490 series instructions. The CAU contained the same basic register stack, in the first 128 words of addressable memory, as previous generations of 1100 Series machines, but since these registers were implemented with the same ECL chips as the rest of the system, the registers did not require parity to be generated/checked with each write/read. The IOU, or Input/Output Unit was modular in design and could be configured with different Channel Modules to support varying I/O requirements. The Word Channel Module included four 1100 Series (parallel) Word Channels. Block Multiplexer and Byte Channel Modules allowed direct connection of high-speed disk/tape systems, and low speed printers, etc. respectively. The Control/Maintenance Panel was now on the SIU, and provided a minimum of indicator/buttons since the system incorporated a mini-computer, based on the BC/7 (business computer) as a maintenance processor. This was used to load microcode, and for diagnostic purposes. The CAU, IOU, and SIU units were implemented using emitter-coupled logic (ECL) on high density multi-layer PC boards. The ECL circuitry utilized DC voltages of +0 and -2 volts, with the CAU requiring four 50 amp -2 volt power supplies. Power was 400 Hz, to reduce large scale DC power supplies. The 400 Hz power was supplied by a motor/alternator, because even though solid state 400 Hz inverters were available, they were not considered reliable enough to meet the system uptime requirements.
An 1100/84 Multiprocessor 4x2 system, in two clusters (could be "partitioned" into two separate systems), including four CPU cabinets, two IOU cabinets, two SIU buffer storage units (16K words each) and 2,096K words of Main Memory (backing storage) in four cabinets, two System Maintenance Units (SMU), two Motor Alternators, a transition unit, and two System Consoles at list price was $5,414,871. in October 1980. This configuration could be rented for $127,764 per month, or leased (5 year) for $95,844 per month. Monthly maintenance was $10,235 on this configuration. It was fairly common to discount list prices for large and/or Government customers.
The UNIVAC 1100/60 was introduced in 1979. It replaced the 1108/1106-based 1100/10 and 1100/20 systems.
The 1100/60 System was available in both Single Processor 1100/61 (Model C1) and Dual Processor 1100/62 (Model H1) configurations. It was implemented using custom Sperry Univac designed Micro-Processor Integrated Circuits. Main Storage (524K to 1048K) words per CPU, optional Semiconductor Buffer Storage (up to 8K words per CPU), and the Input/Output Unit (IOU) were contained in CPU cabinet. The IOU (optionally) supported both Block and Word Channels. The system also included a System Support Processor for diagnostic testing and system console support.
An 1100/62 Model E1 (upgraded version) - Medium Performance Multiprocessor Complex - two CPUs with 2K Buffer Storage, two IOUs with one Block Mux, and one Word Channel module (four channels), 1048K words of Main Storage, two System Support Processors, two System Consoles, and a Maintenance Console listed for $889,340. in March 1980. This configuration could be rented for $21,175 per month, or leased (5 year) for $16,780 per month. Monthly maintenance was $3,000 on this configuration. As with the 1100/80 System discounting was common for large and/or Government customers.
The UNIVAC 1100/70 was introduced in 1981. The technology was an upgraded version of the 1100/60 design. It replaced the 1110-based 1100/40 systems.
The UNIVAC 1100/90 was introduced in 1982. As with the 1100/80, it was available with up to four processors, and four I/O units. It was the largest, and final, member of the 1100 Series, and was the only system to be liquid-cooled.
In 1983, Sperry Corporation discontinued the name UNIVAC for their products.
In 1986, Sperry Corporation merged with Burroughs Corporation to become Unisys, and this corporate name change was henceforth reflected in the system names. Each of the systems listed below represents a family with similar characteristics and architecture, with family members having different performance profiles.
In 1996, Unisys introduced the ClearPath IX series. The ClearPath machines are a common platform that implement either the 1100/2200 architecture (the ClearPath IX series) or the Burroughs large systems architecture (the ClearPath NX series). Everything is common except the actual CPUs, which are implemented as ASICs. In addition to the IX (1100/2200) CPUs and the NX (Burroughs large systems) CPU, the architecture had Xeon (and briefly Itanium) CPUs. Unisys' goal was to provide an orderly transition for their 1100/2200 customers to a more modern architecture.
Edited: 2021-06-18 19:33:52